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Scheduling
and mitigate the effects of memory latency. Through close integration
with SOPC Builder, the C2H Compiler can determine the latency
characteristics of the slave ports connected to the accelerator. The
C2H Compiler generates logic to maximize bandwidth for the specific
memories in the system.
Avalon-MM pipelined read transfers increase the bandwidth for
synchronous slave ports that require several cycles of latency to return
data for the first access, but can return data every cycle thereafter. Using
pipelined read transfers, a slave port can begin a new transfer before data
from the previous transfer returns. There are only pipelined read
transfers; Avalon-MM write transfers do not benefit from pipelined
functionality.
The C2H Compiler takes memory latency into account when scheduling
operations, allowing an accelerator to perform nondependent operations
while waiting for data to return from a memory with latency. The master
ports associated with a pointer might connect to multiple slave ports with
different latency properties. In this case, the C2H Compiler uses the
maximum latency of all slave ports.
Figure 3–18 shows the dependency graph for function foo() , shown in
Example 3–32 . This example uses the connection pragma to exclusively
connect a pointer named ptr_in to a memory with two cycles of read
latency. (Refer to section “Master-Slave Connections” on page 3–23 .)
Example 3–32. Early Scheduling of Read Operation with Latency
#pragma altera_accelerate connect_variable
foo/ptr_in to
my_memory_with_two_cycles_read_latency
int foo(int *ptr_in, int x, int y, int z)
{
int xy = x * y;
int xy_plus_z = xy + z;
int ptr_data = *ptr_in;
int prod = ptr_data * xy_plus_z;
return prod;
}
3–38
Nios II C2H Compiler User Guide
9.1
Altera Corporation
November 2009
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